![]() Fixed detection of SPD slot for systems with soldered and removable DIMMs Fixed bug in mapping SPD module index to SMBIOS slot index Fixed detection of SPD modules on systems with > 8 SMBus controllers (eg. Enable SMBus on Intel 801-based chipsets if disabled Added SMBus (SPD) support for Intel Alder Lake-P Added support for retrieving Intel Ice Lake-SP RAM temperature data Added support for retrieving Intel Ice Lake-SP RAM SPD data Added support for retrieving Intel Ice Lake-SP CPU info Fixed ECC error false positives on Intel Atom C2000 chipsets Fixed ECC support for AMD Ryzen Zen 2 chipsets with 2 memory channels Added ECC support for AMD Ryzen Zen 3 50h-5fh chipset Fixed ECC support for Intel Rocket Lake chipset variant Added ECC detection support for multi-socket Intel Ice Lake-SP chipsets ![]() Fixed ECC detection on Intel Ice Lake-SP chipsets Fixed reading ECC error status register for Intel Tiger Lake-H and Alder Lake chipsets Fixed bug in reading ECC error count registers for various Intel/AMD Ryzen chipsets Added support for reporting IBECC errors Fixed detection of MAC address used as unique ID for PXE boot Fixed clock speed measurement failure for ARM chipsets due to cycle count register not being enabled Fixed hammer test incorrectly running in single-sided mode in Free version Fixed 'MAXCPUS' config file parameter not being applied ![]() Added new blacklist flag 'DISABLE_CPUINFO' for disabling CPU info collection Log file name now includes the timestamp By default, DRAM chips are labeled consecutively starting from U0 (eg. Added new config file parameter, 'CPUMAP', to specify the DRAM chip labeling map. This includes mid-test error reporting, graphical UI summary report on test completion and per-DIMM/chip error count table in the HTML report. DIMM (Pro edition)/chip-level (Site Edition) error detection on limited number of hardware platforms. ![]() As this test is experimental, it shall be disabled by default. ![]() The motivation for this test came from discovering a defective RAM module that did not produce errors when accessed via the CPU, but failed when files were read from disk via DMA. This test exercises the disk controller's DMA hardware to perform memory access, bypassing the CPU. Added new experimental memory test as Test 14. ![]()
0 Comments
Leave a Reply.AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |